Passive element memory arrays, such as antifuse diode cell arrays, require a high-voltage and high-current programming voltage source due to the large number of leakage paths in the array and the high voltage required to program the memory. The write power increases the temperature of the memory cells. As the temperature of the memory cell diodes increases, the diode leakage current increases. Increased leakage may cause a drop in voltage available to program memory, and may result in incomplete or unreliable programming.
There is a need to maximize the bandwidth of read, write, and erase operations while avoiding incomplete or unreliable programming.
The present invention is defined by the following claims, and nothing in this section should be taken as a limitation on those claims. In general, the invention is directed to a direct method of selecting the optimal number of sections for simultaneous write, read, or (in the case of rewriteable memory) erase operations based on actual, rather than projected, conditions on the circuit.
The preferred embodiments described below provide for a method of selecting a number of sections to concurrently read, write, or erase. The number is based on a direct measurement of a condition of the circuit. One preferred embodiment involves biasing a test number of sections, and obtaining a circuit state value, which is responsive to the number of sections biased. The method then involves comparing the circuit state value to a reference parameter. Finally, a number of sections to write, read, or erase is selected based on the result of the comparison. In another preferred embodiment, the process of biasing sections, comparing a circuit state value with a reference parameter, and selecting a number of sections to write, read, or erase can be repeated, with a different number of sections biased for each repetition.
Another preferred embodiment provides for a memory device employing a method of selecting a number of sections to concurrently read, write, or erase. The number is based on a direct measurement of a condition of the circuit. One preferred embodiment provides for a memory device employing a method which involves biasing a test number of sections, and obtaining a circuit state value, which is responsive to the number of sections biased. The method then involves comparing the circuit state value to a reference parameter. Finally, a number of sections to write, read, or erase is selected based on the result of the comparison. In another preferred embodiment, the process of biasing sections, comparing a circuit state value with a reference parameter, and selecting a number of sections to write, read, or erase can be repeated, with a different number of sections biased for each repetition.
Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
The preferred embodiments will now be described with reference to the attached drawings.